#ifndef MAC_REGS_H
#define MAC_REGS_H

#include <stdint.h>

#define DWMAC_REGS_BIT32(bit) \
  ((uint32_t) (((uint32_t) 1) << (bit)))

#define DWMAC_REGS_MSK32(first_bit, last_bit) \
  ((uint32_t) ((DWMAC_REGS_BIT32((last_bit) - (first_bit) + 1) - 1) << (first_bit)))

#define DWMAC_REGS_FLD32(val, first_bit, last_bit) \
  ((uint32_t) \
    ((((uint32_t) (val)) << (first_bit)) & DWMAC_REGS_MSK32(first_bit, last_bit)))

#define DWMAC_REGS_FLD32GET(reg, first_bit, last_bit) \
  ((uint32_t) (((reg) & DWMAC_REGS_MSK32(first_bit, last_bit)) >> (first_bit)))

#define DWMAC_REGS_FLD32SET(reg, val, first_bit, last_bit) \
  ((uint32_t) (((reg) & ~DWMAC_REGS_MSK32(first_bit, last_bit)) \
    | DWMAC_REGS_FLD32(val, first_bit, last_bit)))

typedef struct {
	uint32_t high;
#define MAC_HIGH_ADDRHI(val) DWMAC_REGS_FLD32(val, 0, 15)
#define MAC_HIGH_ADDRHI_GET(reg) DWMAC_REGS_FLD32GET(reg, 0, 15)
#define MAC_HIGH_ADDRHI_SET(reg, val) DWMAC_REGS_FLD32SET(reg, val, 0, 15)
#define MAC_HIGH_MBC0 DWMAC_REGS_BIT32(24)
#define MAC_HIGH_MBC1 DWMAC_REGS_BIT32(25)
#define MAC_HIGH_MBC2 DWMAC_REGS_BIT32(26)
#define MAC_HIGH_MBC3 DWMAC_REGS_BIT32(27)
#define MAC_HIGH_MBC4 DWMAC_REGS_BIT32(28)
#define MAC_HIGH_MBC5 DWMAC_REGS_BIT32(29)
#define MAC_HIGH_SA DWMAC_REGS_BIT32(30)
#define MAC_HIGH_AE DWMAC_REGS_BIT32(31)
	uint32_t low;
#define MAC_LOW_ADDRLO(val) DWMAC_REGS_FLD32(val, 0, 32)
#define MAC_LOW_ADDRLO_GET(reg) DWMAC_REGS_FLD32GET(reg, 0, 32)
#define MAC_LOW_ADDRLO_SET(reg, val) DWMAC_REGS_FLD32SET(reg, val, 0, 32)
} mac;

typedef struct {
	uint32_t mac_configuration;
#define MACGRP_MAC_CONFIGURATION_PRELEN(val) DWMAC_REGS_FLD32(val, 0, 1)
#define MACGRP_MAC_CONFIGURATION_PRELEN_GET(reg) DWMAC_REGS_FLD32GET(reg, 0, 1)
#define MACGRP_MAC_CONFIGURATION_PRELEN_SET(reg, val) DWMAC_REGS_FLD32SET(reg, val, 0, 1)
#define MACGRP_MAC_CONFIGURATION_RE DWMAC_REGS_BIT32(2)
#define MACGRP_MAC_CONFIGURATION_TE DWMAC_REGS_BIT32(3)
#define MACGRP_MAC_CONFIGURATION_DC DWMAC_REGS_BIT32(4)
#define MACGRP_MAC_CONFIGURATION_BL(val) DWMAC_REGS_FLD32(val, 5, 6)
#define MACGRP_MAC_CONFIGURATION_BL_GET(reg) DWMAC_REGS_FLD32GET(reg, 5, 6)
#define MACGRP_MAC_CONFIGURATION_BL_SET(reg, val) DWMAC_REGS_FLD32SET(reg, val, 5, 6)
#define MACGRP_MAC_CONFIGURATION_ACS DWMAC_REGS_BIT32(7)
#define MACGRP_MAC_CONFIGURATION_LUD DWMAC_REGS_BIT32(8)
#define MACGRP_MAC_CONFIGURATION_DR DWMAC_REGS_BIT32(9)
#define MACGRP_MAC_CONFIGURATION_IPC DWMAC_REGS_BIT32(10)
#define MACGRP_MAC_CONFIGURATION_DM DWMAC_REGS_BIT32(11)
#define MACGRP_MAC_CONFIGURATION_LM DWMAC_REGS_BIT32(12)
#define MACGRP_MAC_CONFIGURATION_DO DWMAC_REGS_BIT32(13)
#define MACGRP_MAC_CONFIGURATION_FES DWMAC_REGS_BIT32(14)
#define MACGRP_MAC_CONFIGURATION_PS DWMAC_REGS_BIT32(15)
#define MACGRP_MAC_CONFIGURATION_DCRS DWMAC_REGS_BIT32(16)
#define MACGRP_MAC_CONFIGURATION_IFG(val) DWMAC_REGS_FLD32(val, 17, 19)
#define MACGRP_MAC_CONFIGURATION_IFG_GET(reg) DWMAC_REGS_FLD32GET(reg, 17, 19)
#define MACGRP_MAC_CONFIGURATION_IFG_SET(reg, val) DWMAC_REGS_FLD32SET(reg, val, 17, 19)
#define MACGRP_MAC_CONFIGURATION_JE DWMAC_REGS_BIT32(20)
#define MACGRP_MAC_CONFIGURATION_BE DWMAC_REGS_BIT32(21)
#define MACGRP_MAC_CONFIGURATION_JD DWMAC_REGS_BIT32(22)
#define MACGRP_MAC_CONFIGURATION_WD DWMAC_REGS_BIT32(23)
#define MACGRP_MAC_CONFIGURATION_TC DWMAC_REGS_BIT32(24)
#define MACGRP_MAC_CONFIGURATION_CST DWMAC_REGS_BIT32(25)
#define MACGRP_MAC_CONFIGURATION_TWOKPE DWMAC_REGS_BIT32(27)
	uint32_t mac_frame_filter;
#define MACGRP_MAC_FRAME_FILTER_PR DWMAC_REGS_BIT32(0)
#define MACGRP_MAC_FRAME_FILTER_HUC DWMAC_REGS_BIT32(1)
#define MACGRP_MAC_FRAME_FILTER_HMC DWMAC_REGS_BIT32(2)
#define MACGRP_MAC_FRAME_FILTER_DAIF DWMAC_REGS_BIT32(3)
#define MACGRP_MAC_FRAME_FILTER_PM DWMAC_REGS_BIT32(4)
#define MACGRP_MAC_FRAME_FILTER_DBF DWMAC_REGS_BIT32(5)
#define MACGRP_MAC_FRAME_FILTER_PCF(val) DWMAC_REGS_FLD32(val, 6, 7)
#define MACGRP_MAC_FRAME_FILTER_PCF_GET(reg) DWMAC_REGS_FLD32GET(reg, 6, 7)
#define MACGRP_MAC_FRAME_FILTER_PCF_SET(reg, val) DWMAC_REGS_FLD32SET(reg, val, 6, 7)
#define MACGRP_MAC_FRAME_FILTER_SAIF DWMAC_REGS_BIT32(8)
#define MACGRP_MAC_FRAME_FILTER_SAF DWMAC_REGS_BIT32(9)
#define MACGRP_MAC_FRAME_FILTER_HPF DWMAC_REGS_BIT32(10)
#define MACGRP_MAC_FRAME_FILTER_VTFE DWMAC_REGS_BIT32(16)
#define MACGRP_MAC_FRAME_FILTER_IPFE DWMAC_REGS_BIT32(20)
#define MACGRP_MAC_FRAME_FILTER_DNTU DWMAC_REGS_BIT32(21)
#define MACGRP_MAC_FRAME_FILTER_RA DWMAC_REGS_BIT32(31)
	uint32_t reserved_08[2];
	uint32_t gmii_address;
#define MACGRP_GMII_ADDRESS_GMII_BUSY DWMAC_REGS_BIT32(0)
#define MACGRP_GMII_ADDRESS_GMII_WRITE DWMAC_REGS_BIT32(1)
#define MACGRP_GMII_ADDRESS_CSR_CLOCK_RANGE(val) DWMAC_REGS_FLD32(val, 2, 5)
#define MACGRP_GMII_ADDRESS_CSR_CLOCK_RANGE_GET(reg) DWMAC_REGS_FLD32GET(reg, 2, 5)
#define MACGRP_GMII_ADDRESS_CSR_CLOCK_RANGE_SET(reg, val) DWMAC_REGS_FLD32SET(reg, val, 2, 5)
#define MACGRP_GMII_ADDRESS_GMII_REGISTER(val) DWMAC_REGS_FLD32(val, 6, 10)
#define MACGRP_GMII_ADDRESS_GMII_REGISTER_GET(reg) DWMAC_REGS_FLD32GET(reg, 6, 10)
#define MACGRP_GMII_ADDRESS_GMII_REGISTER_SET(reg, val) DWMAC_REGS_FLD32SET(reg, val, 6, 10)
#define MACGRP_GMII_ADDRESS_PHYSICAL_LAYER_ADDRESS(val) DWMAC_REGS_FLD32(val, 11, 15)
#define MACGRP_GMII_ADDRESS_PHYSICAL_LAYER_ADDRESS_GET(reg) DWMAC_REGS_FLD32GET(reg, 11, 15)
#define MACGRP_GMII_ADDRESS_PHYSICAL_LAYER_ADDRESS_SET(reg, val) DWMAC_REGS_FLD32SET(reg, val, 11, 15)
	uint32_t gmii_data;
#define MACGRP_GMII_DATA_GMII_DATA(val) DWMAC_REGS_FLD32(val, 0, 15)
#define MACGRP_GMII_DATA_GMII_DATA_GET(reg) DWMAC_REGS_FLD32GET(reg, 0, 15)
#define MACGRP_GMII_DATA_GMII_DATA_SET(reg, val) DWMAC_REGS_FLD32SET(reg, val, 0, 15)
	uint32_t reserved_18[9];
	uint32_t interrupt_mask;
#define MACGRP_INTERRUPT_MASK_RGSMIIIM DWMAC_REGS_BIT32(0)
#define MACGRP_INTERRUPT_MASK_PCSLCHGIM DWMAC_REGS_BIT32(1)
#define MACGRP_INTERRUPT_MASK_PCSANCIM DWMAC_REGS_BIT32(2)
#define MACGRP_INTERRUPT_MASK_TSIM DWMAC_REGS_BIT32(9)
#define MACGRP_INTERRUPT_MASK_LPIIM DWMAC_REGS_BIT32(10)
	mac mac_addr0_15[16];
	uint32_t reserved_c0[16];
	uint32_t mmc_control;
#define MACGRP_MMC_CONTROL_CNTRST DWMAC_REGS_BIT32(0)
#define MACGRP_MMC_CONTROL_CNTSTOPRO DWMAC_REGS_BIT32(1)
#define MACGRP_MMC_CONTROL_RSTONRD DWMAC_REGS_BIT32(2)
#define MACGRP_MMC_CONTROL_CNTFREEZ DWMAC_REGS_BIT32(3)
#define MACGRP_MMC_CONTROL_CNTPRST DWMAC_REGS_BIT32(4)
#define MACGRP_MMC_CONTROL_CNTPRSTLVL DWMAC_REGS_BIT32(5)
#define MACGRP_MMC_CONTROL_UCDBC DWMAC_REGS_BIT32(8)
	uint32_t mmc_receive_interrupt;
#define MACGRP_MMC_RECEIVE_INTERRUPT_RXGBFRMIS DWMAC_REGS_BIT32(0)
#define MACGRP_MMC_RECEIVE_INTERRUPT_RXGBOCTIS DWMAC_REGS_BIT32(1)
#define MACGRP_MMC_RECEIVE_INTERRUPT_RXGOCTIS DWMAC_REGS_BIT32(2)
#define MACGRP_MMC_RECEIVE_INTERRUPT_RXBCGFIS DWMAC_REGS_BIT32(3)
#define MACGRP_MMC_RECEIVE_INTERRUPT_RXMCGFIS DWMAC_REGS_BIT32(4)
#define MACGRP_MMC_RECEIVE_INTERRUPT_RXCRCERFIS DWMAC_REGS_BIT32(5)
#define MACGRP_MMC_RECEIVE_INTERRUPT_RXALGNERFIS DWMAC_REGS_BIT32(6)
#define MACGRP_MMC_RECEIVE_INTERRUPT_RXRUNTFIS DWMAC_REGS_BIT32(7)
#define MACGRP_MMC_RECEIVE_INTERRUPT_RXJABERFIS DWMAC_REGS_BIT32(8)
#define MACGRP_MMC_RECEIVE_INTERRUPT_RXUSIZEGFIS DWMAC_REGS_BIT32(9)
#define MACGRP_MMC_RECEIVE_INTERRUPT_RXOSIZEGFIS DWMAC_REGS_BIT32(10)
#define MACGRP_MMC_RECEIVE_INTERRUPT_RX64OCTGBFIS DWMAC_REGS_BIT32(11)
#define MACGRP_MMC_RECEIVE_INTERRUPT_RX65T127OCTGBFIS DWMAC_REGS_BIT32(12)
#define MACGRP_MMC_RECEIVE_INTERRUPT_RX128T255OCTGBFIS DWMAC_REGS_BIT32(13)
#define MACGRP_MMC_RECEIVE_INTERRUPT_RX256T511OCTGBFIS DWMAC_REGS_BIT32(14)
#define MACGRP_MMC_RECEIVE_INTERRUPT_RX512T1023OCTGBFIS DWMAC_REGS_BIT32(15)
#define MACGRP_MMC_RECEIVE_INTERRUPT_RX1024TMAXOCTGBFIS DWMAC_REGS_BIT32(16)
#define MACGRP_MMC_RECEIVE_INTERRUPT_RXUCGFIS DWMAC_REGS_BIT32(17)
#define MACGRP_MMC_RECEIVE_INTERRUPT_RXLENERFIS DWMAC_REGS_BIT32(18)
#define MACGRP_MMC_RECEIVE_INTERRUPT_RXORANGEFIS DWMAC_REGS_BIT32(19)
#define MACGRP_MMC_RECEIVE_INTERRUPT_RXPAUSFIS DWMAC_REGS_BIT32(20)
#define MACGRP_MMC_RECEIVE_INTERRUPT_RXFOVFIS DWMAC_REGS_BIT32(21)
#define MACGRP_MMC_RECEIVE_INTERRUPT_RXVLANGBFIS DWMAC_REGS_BIT32(22)
#define MACGRP_MMC_RECEIVE_INTERRUPT_RXWDOGFIS DWMAC_REGS_BIT32(23)
#define MACGRP_MMC_RECEIVE_INTERRUPT_RXRCVERRFIS DWMAC_REGS_BIT32(24)
#define MACGRP_MMC_RECEIVE_INTERRUPT_RXCTRLFIS DWMAC_REGS_BIT32(25)
	uint32_t mmc_transmit_interrupt;
#define MACGRP_MMC_TRANSMIT_INTERRUPT_TXGBOCTIS DWMAC_REGS_BIT32(0)
#define MACGRP_MMC_TRANSMIT_INTERRUPT_TXGBFRMIS DWMAC_REGS_BIT32(1)
#define MACGRP_MMC_TRANSMIT_INTERRUPT_TXBCGFIS DWMAC_REGS_BIT32(2)
#define MACGRP_MMC_TRANSMIT_INTERRUPT_TXMCGFIS DWMAC_REGS_BIT32(3)
#define MACGRP_MMC_TRANSMIT_INTERRUPT_TX64OCTGBFIS DWMAC_REGS_BIT32(4)
#define MACGRP_MMC_TRANSMIT_INTERRUPT_TX65T127OCTGBFIS DWMAC_REGS_BIT32(5)
#define MACGRP_MMC_TRANSMIT_INTERRUPT_TX128T255OCTGBFIS DWMAC_REGS_BIT32(6)
#define MACGRP_MMC_TRANSMIT_INTERRUPT_TX256T511OCTGBFIS DWMAC_REGS_BIT32(7)
#define MACGRP_MMC_TRANSMIT_INTERRUPT_TX512T1023OCTGBFIS DWMAC_REGS_BIT32(8)
#define MACGRP_MMC_TRANSMIT_INTERRUPT_TX1024TMAXOCTGBFIS DWMAC_REGS_BIT32(9)
#define MACGRP_MMC_TRANSMIT_INTERRUPT_TXUCGBFIS DWMAC_REGS_BIT32(10)
#define MACGRP_MMC_TRANSMIT_INTERRUPT_TXMCGBFIS DWMAC_REGS_BIT32(11)
#define MACGRP_MMC_TRANSMIT_INTERRUPT_TXBCGBFIS DWMAC_REGS_BIT32(12)
#define MACGRP_MMC_TRANSMIT_INTERRUPT_TXUFLOWERFIS DWMAC_REGS_BIT32(13)
#define MACGRP_MMC_TRANSMIT_INTERRUPT_TXSCOLGFIS DWMAC_REGS_BIT32(14)
#define MACGRP_MMC_TRANSMIT_INTERRUPT_TXMCOLGFIS DWMAC_REGS_BIT32(15)
#define MACGRP_MMC_TRANSMIT_INTERRUPT_TXDEFFIS DWMAC_REGS_BIT32(16)
#define MACGRP_MMC_TRANSMIT_INTERRUPT_TXLATCOLFIS DWMAC_REGS_BIT32(17)
#define MACGRP_MMC_TRANSMIT_INTERRUPT_TXEXCOLFIS DWMAC_REGS_BIT32(18)
#define MACGRP_MMC_TRANSMIT_INTERRUPT_TXCARERFIS DWMAC_REGS_BIT32(19)
#define MACGRP_MMC_TRANSMIT_INTERRUPT_TXGOCTIS DWMAC_REGS_BIT32(20)
#define MACGRP_MMC_TRANSMIT_INTERRUPT_TXGFRMIS DWMAC_REGS_BIT32(21)
#define MACGRP_MMC_TRANSMIT_INTERRUPT_TXEXDEFFIS DWMAC_REGS_BIT32(22)
#define MACGRP_MMC_TRANSMIT_INTERRUPT_TXPAUSFIS DWMAC_REGS_BIT32(23)
#define MACGRP_MMC_TRANSMIT_INTERRUPT_TXVLANGFIS DWMAC_REGS_BIT32(24)
#define MACGRP_MMC_TRANSMIT_INTERRUPT_TXOSIZEGFIS DWMAC_REGS_BIT32(25)
	uint32_t mmc_receive_interrupt_mask;
#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXGBFRMIM DWMAC_REGS_BIT32(0)
#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXGBOCTIM DWMAC_REGS_BIT32(1)
#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXGOCTIM DWMAC_REGS_BIT32(2)
#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXBCGFIM DWMAC_REGS_BIT32(3)
#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXMCGFIM DWMAC_REGS_BIT32(4)
#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXCRCERFIM DWMAC_REGS_BIT32(5)
#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXALGNERFIM DWMAC_REGS_BIT32(6)
#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXRUNTFIM DWMAC_REGS_BIT32(7)
#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXJABERFIM DWMAC_REGS_BIT32(8)
#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXUSIZEGFIM DWMAC_REGS_BIT32(9)
#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXOSIZEGFIM DWMAC_REGS_BIT32(10)
#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RX64OCTGBFIM DWMAC_REGS_BIT32(11)
#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RX65T127OCTGBFIM DWMAC_REGS_BIT32(12)
#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RX128T255OCTGBFIM DWMAC_REGS_BIT32(13)
#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RX256T511OCTGBFIM DWMAC_REGS_BIT32(14)
#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RX512T1023OCTGBFIM DWMAC_REGS_BIT32(15)
#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RX1024TMAXOCTGBFIM DWMAC_REGS_BIT32(16)
#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXUCGFIM DWMAC_REGS_BIT32(17)
#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXLENERFIM DWMAC_REGS_BIT32(18)
#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXORANGEFIM DWMAC_REGS_BIT32(19)
#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXPAUSFIM DWMAC_REGS_BIT32(20)
#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXFOVFIM DWMAC_REGS_BIT32(21)
#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXVLANGBFIM DWMAC_REGS_BIT32(22)
#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXWDOGFIM DWMAC_REGS_BIT32(23)
#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXRCVERRFIM DWMAC_REGS_BIT32(24)
#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXCTRLFIM DWMAC_REGS_BIT32(25)
	uint32_t mmc_transmit_interrupt_mask;
#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXGBOCTIM DWMAC_REGS_BIT32(0)
#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXGBFRMIM DWMAC_REGS_BIT32(1)
#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXBCGFIM DWMAC_REGS_BIT32(2)
#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXMCGFIM DWMAC_REGS_BIT32(3)
#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TX64OCTGBFIM DWMAC_REGS_BIT32(4)
#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TX65T127OCTGBFIM DWMAC_REGS_BIT32(5)
#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TX128T255OCTGBFIM DWMAC_REGS_BIT32(6)
#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TX256T511OCTGBFIM DWMAC_REGS_BIT32(7)
#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TX512T1023OCTGBFIM DWMAC_REGS_BIT32(8)
#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TX1024TMAXOCTGBFIM DWMAC_REGS_BIT32(9)
#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXUCGBFIM DWMAC_REGS_BIT32(10)
#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXMCGBFIM DWMAC_REGS_BIT32(11)
#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXBCGBFIM DWMAC_REGS_BIT32(12)
#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXUFLOWERFIM DWMAC_REGS_BIT32(13)
#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXSCOLGFIM DWMAC_REGS_BIT32(14)
#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXMCOLGFIM DWMAC_REGS_BIT32(15)
#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXDEFFIM DWMAC_REGS_BIT32(16)
#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXLATCOLFIM DWMAC_REGS_BIT32(17)
#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXEXCOLFIM DWMAC_REGS_BIT32(18)
#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXCARERFIM DWMAC_REGS_BIT32(19)
#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXGOCTIM DWMAC_REGS_BIT32(20)
#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXGFRMIM DWMAC_REGS_BIT32(21)
#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXEXDEFFIM DWMAC_REGS_BIT32(22)
#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXPAUSFIM DWMAC_REGS_BIT32(23)
#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXVLANGFIM DWMAC_REGS_BIT32(24)
#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXOSIZEGFIM DWMAC_REGS_BIT32(25)
	uint32_t txoctetcount_gb;
	uint32_t txframecount_gb;
	uint32_t txbroadcastframes_g;
	uint32_t txmulticastframes_g;
	uint32_t tx64octets_gb;
	uint32_t tx65to127octets_gb;
	uint32_t tx128to255octets_gb;
	uint32_t tx256to511octets_gb;
	uint32_t tx512to1023octets_gb;
	uint32_t tx1024tomaxoctets_gb;
	uint32_t txunicastframes_gb;
	uint32_t txmulticastframes_gb;
	uint32_t txbroadcastframes_gb;
	uint32_t txunderflowerror;
	uint32_t txsinglecol_g;
	uint32_t txmulticol_g;
	uint32_t txdeferred;
	uint32_t txlatecol;
	uint32_t txexesscol;
	uint32_t txcarriererr;
	uint32_t txoctetcnt;
	uint32_t txframecount_g;
	uint32_t txexcessdef;
	uint32_t txpauseframes;
	uint32_t txvlanframes_g;
	uint32_t txoversize_g;
	uint32_t reserved_17c;
	uint32_t rxframecount_gb;
	uint32_t rxoctetcount_gb;
	uint32_t rxoctetcount_g;
	uint32_t rxbroadcastframes_g;
	uint32_t rxmulticastframes_g;
	uint32_t rxcrcerror;
	uint32_t rxalignmenterror;
	uint32_t rxrunterror;
	uint32_t rxjabbererror;
	uint32_t rxundersize_g;
	uint32_t rxoversize_g;
	uint32_t rx64octets_gb;
	uint32_t rx65to127octets_gb;
	uint32_t rx128to255octets_gb;
	uint32_t rx256to511octets_gb;
	uint32_t rx512to1023octets_gb;
	uint32_t rx1024tomaxoctets_gb;
	uint32_t rxunicastframes_g;
	uint32_t rxlengtherror;
	uint32_t rxoutofrangetype;
	uint32_t rxpauseframes;
	uint32_t rxfifooverflow;
	uint32_t rxvlanframes_gb;
	uint32_t rxwatchdogerror;
	uint32_t rxrcverror;
	uint32_t rxctrlframes_g;
	uint32_t reserved_1e8[6];
	uint32_t mmc_ipc_receive_interrupt_mask;
#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4GFIM DWMAC_REGS_BIT32(0)
#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4HERFIM DWMAC_REGS_BIT32(1)
#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4NOPAYFIM DWMAC_REGS_BIT32(2)
#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4FRAGFIM DWMAC_REGS_BIT32(3)
#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4UDSBLFIM DWMAC_REGS_BIT32(4)
#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6GFIM DWMAC_REGS_BIT32(5)
#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6HERFIM DWMAC_REGS_BIT32(6)
#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6NOPAYFIM DWMAC_REGS_BIT32(7)
#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPGFIM DWMAC_REGS_BIT32(8)
#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPERFIM DWMAC_REGS_BIT32(9)
#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPGFIM DWMAC_REGS_BIT32(10)
#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPERFIM DWMAC_REGS_BIT32(11)
#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPGFIM DWMAC_REGS_BIT32(12)
#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPERFIM DWMAC_REGS_BIT32(13)
#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4GOIM DWMAC_REGS_BIT32(16)
#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4HEROIM DWMAC_REGS_BIT32(17)
#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4NOPAYOIM DWMAC_REGS_BIT32(18)
#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4FRAGOIM DWMAC_REGS_BIT32(19)
#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4UDSBLOIM DWMAC_REGS_BIT32(20)
#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6GOIM DWMAC_REGS_BIT32(21)
#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6HEROIM DWMAC_REGS_BIT32(22)
#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6NOPAYOIM DWMAC_REGS_BIT32(23)
#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPGOIM DWMAC_REGS_BIT32(24)
#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPEROIM DWMAC_REGS_BIT32(25)
#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPGOIM DWMAC_REGS_BIT32(26)
#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPEROIM DWMAC_REGS_BIT32(27)
#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPGOIM DWMAC_REGS_BIT32(28)
#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPEROIM DWMAC_REGS_BIT32(29)
	uint32_t reserved_204;
	uint32_t mmc_ipc_receive_interrupt;
#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4GFIS DWMAC_REGS_BIT32(0)
#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4HERFIS DWMAC_REGS_BIT32(1)
#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4NOPAYFIS DWMAC_REGS_BIT32(2)
#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4FRAGFIS DWMAC_REGS_BIT32(3)
#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4UDSBLFIS DWMAC_REGS_BIT32(4)
#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6GFIS DWMAC_REGS_BIT32(5)
#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6HERFIS DWMAC_REGS_BIT32(6)
#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6NOPAYFIS DWMAC_REGS_BIT32(7)
#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXUDPGFIS DWMAC_REGS_BIT32(8)
#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXUDPERFIS DWMAC_REGS_BIT32(9)
#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXTCPGFIS DWMAC_REGS_BIT32(10)
#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXTCPERFIS DWMAC_REGS_BIT32(11)
#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXICMPGFIS DWMAC_REGS_BIT32(12)
#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXICMPERFIS DWMAC_REGS_BIT32(13)
#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4GOIS DWMAC_REGS_BIT32(16)
#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4HEROIS DWMAC_REGS_BIT32(17)
#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4NOPAYOIS DWMAC_REGS_BIT32(18)
#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4FRAGOIS DWMAC_REGS_BIT32(19)
#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4UDSBLOIS DWMAC_REGS_BIT32(20)
#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6GOIS DWMAC_REGS_BIT32(21)
#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6HEROIS DWMAC_REGS_BIT32(22)
#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6NOPAYOIS DWMAC_REGS_BIT32(23)
#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXUDPGOIS DWMAC_REGS_BIT32(24)
#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXUDPEROIS DWMAC_REGS_BIT32(25)
#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXTCPGOIS DWMAC_REGS_BIT32(26)
#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXTCPEROIS DWMAC_REGS_BIT32(27)
#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXICMPGOIS DWMAC_REGS_BIT32(28)
#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXICMPEROIS DWMAC_REGS_BIT32(29)
	uint32_t reserved_20c;
	uint32_t rxipv4_gd_frms;
	uint32_t rxipv4_hdrerr_frms;
	uint32_t rxipv4_nopay_frms;
	uint32_t rxipv4_frag_frms;
	uint32_t rxipv4_udsbl_frms;
	uint32_t rxipv6_gd_frms;
	uint32_t rxipv6_hdrerr_frms;
	uint32_t rxipv6_nopay_frms;
	uint32_t rxudp_gd_frms;
	uint32_t rxudp_err_frms;
	uint32_t rxtcp_gd_frms;
	uint32_t rxtcp_err_frms;
	uint32_t rxicmp_gd_frms;
	uint32_t rxicmp_err_frms;
	uint32_t reserved_248[2];
	uint32_t rxipv4_gd_octets;
	uint32_t rxipv4_hdrerr_octets;
	uint32_t rxipv4_nopay_octets;
	uint32_t rxipv4_frag_octets;
	uint32_t rxipv4_udsbl_octets;
	uint32_t rxipv6_gd_octets;
	uint32_t rxipv6_hdrerr_octets;
	uint32_t rxipv6_nopay_octets;
	uint32_t rxudp_gd_octets;
	uint32_t rxudp_err_octets;
	uint32_t rxtcp_gd_octets;
	uint32_t rxtcperroctets;
	uint32_t rxicmp_gd_octets;
	uint32_t rxicmp_err_octets;
	uint32_t reserved_288[158];
	uint32_t hash_table_reg[8];
	uint32_t reserved_520[184];
	mac mac_addr16_127[112];
} macgrp;

typedef struct {
	uint32_t bus_mode;
#define DMAGRP_BUS_MODE_SWR DWMAC_REGS_BIT32(0)
#define DMAGRP_BUS_MODE_DSL(val) DWMAC_REGS_FLD32(val, 2, 6)
#define DMAGRP_BUS_MODE_DSL_GET(reg) DWMAC_REGS_FLD32GET(reg, 2, 6)
#define DMAGRP_BUS_MODE_DSL_SET(reg, val) DWMAC_REGS_FLD32SET(reg, val, 2, 6)
#define DMAGRP_BUS_MODE_ATDS DWMAC_REGS_BIT32(7)
#define DMAGRP_BUS_MODE_PBL(val) DWMAC_REGS_FLD32(val, 8, 13)
#define DMAGRP_BUS_MODE_PBL_GET(reg) DWMAC_REGS_FLD32GET(reg, 8, 13)
#define DMAGRP_BUS_MODE_PBL_SET(reg, val) DWMAC_REGS_FLD32SET(reg, val, 8, 13)
#define DMAGRP_BUS_MODE_FB DWMAC_REGS_BIT32(16)
#define DMAGRP_BUS_MODE_RPBL(val) DWMAC_REGS_FLD32(val, 17, 22)
#define DMAGRP_BUS_MODE_RPBL_GET(reg) DWMAC_REGS_FLD32GET(reg, 17, 22)
#define DMAGRP_BUS_MODE_RPBL_SET(reg, val) DWMAC_REGS_FLD32SET(reg, val, 17, 22)
#define DMAGRP_BUS_MODE_USP DWMAC_REGS_BIT32(23)
#define DMAGRP_BUS_MODE_EIGHTXPBL DWMAC_REGS_BIT32(24)
#define DMAGRP_BUS_MODE_AAL DWMAC_REGS_BIT32(25)
#define DMAGRP_BUS_MODE_MB DWMAC_REGS_BIT32(26)
	uint32_t transmit_poll_demand;
#define DMAGRP_TRANSMIT_POLL_DEMAND_TPD(val) DWMAC_REGS_FLD32(val, 0, 31)
#define DMAGRP_TRANSMIT_POLL_DEMAND_TPD_GET(reg) DWMAC_REGS_FLD32GET(reg, 0, 31)
#define DMAGRP_TRANSMIT_POLL_DEMAND_TPD_SET(reg, val) DWMAC_REGS_FLD32SET(reg, val, 0, 31)
	uint32_t receive_poll_demand;
#define DMAGRP_RECEIVE_POLL_DEMAND_RPD(val) DWMAC_REGS_FLD32(val, 0, 31)
#define DMAGRP_RECEIVE_POLL_DEMAND_RPD_GET(reg) DWMAC_REGS_FLD32GET(reg, 0, 31)
#define DMAGRP_RECEIVE_POLL_DEMAND_RPD_SET(reg, val) DWMAC_REGS_FLD32SET(reg, val, 0, 31)
	uint32_t receive_descr_list_addr;
#define DMAGRP_RECEIVE_DESCR_LIST_ADDR_RDESLA_32BIT(val) DWMAC_REGS_FLD32(val, 2, 31)
#define DMAGRP_RECEIVE_DESCR_LIST_ADDR_RDESLA_32BIT_GET(reg) DWMAC_REGS_FLD32GET(reg, 2, 31)
#define DMAGRP_RECEIVE_DESCR_LIST_ADDR_RDESLA_32BIT_SET(reg, val) DWMAC_REGS_FLD32SET(reg, val, 2, 31)
	uint32_t transmit_descr_list_addr;
#define DMAGRP_TRANSMIT_DESCR_LIST_ADDR_TDESLA_32BIT(val) DWMAC_REGS_FLD32(val, 2, 31)
#define DMAGRP_TRANSMIT_DESCR_LIST_ADDR_TDESLA_32BIT_GET(reg) DWMAC_REGS_FLD32GET(reg, 2, 31)
#define DMAGRP_TRANSMIT_DESCR_LIST_ADDR_TDESLA_32BIT_SET(reg, val) DWMAC_REGS_FLD32SET(reg, val, 2, 31)
	uint32_t status;
#define DMAGRP_STATUS_TI DWMAC_REGS_BIT32(0)
#define DMAGRP_STATUS_TPS DWMAC_REGS_BIT32(1)
#define DMAGRP_STATUS_TU DWMAC_REGS_BIT32(2)
#define DMAGRP_STATUS_TJT DWMAC_REGS_BIT32(3)
#define DMAGRP_STATUS_OVF DWMAC_REGS_BIT32(4)
#define DMAGRP_STATUS_UNF DWMAC_REGS_BIT32(5)
#define DMAGRP_STATUS_RI DWMAC_REGS_BIT32(6)
#define DMAGRP_STATUS_RU DWMAC_REGS_BIT32(7)
#define DMAGRP_STATUS_RPS DWMAC_REGS_BIT32(8)
#define DMAGRP_STATUS_RWT DWMAC_REGS_BIT32(9)
#define DMAGRP_STATUS_ETI DWMAC_REGS_BIT32(10)
#define DMAGRP_STATUS_FBI DWMAC_REGS_BIT32(13)
#define DMAGRP_STATUS_ERI DWMAC_REGS_BIT32(14)
#define DMAGRP_STATUS_AIS DWMAC_REGS_BIT32(15)
#define DMAGRP_STATUS_NIS DWMAC_REGS_BIT32(16)
#define DMAGRP_STATUS_RS(val) DWMAC_REGS_FLD32(val, 17, 19)
#define DMAGRP_STATUS_RS_GET(reg) DWMAC_REGS_FLD32GET(reg, 17, 19)
#define DMAGRP_STATUS_RS_SET(reg, val) DWMAC_REGS_FLD32SET(reg, val, 17, 19)
#define DMAGRP_STATUS_TS(val) DWMAC_REGS_FLD32(val, 20, 22)
#define DMAGRP_STATUS_TS_GET(reg) DWMAC_REGS_FLD32GET(reg, 20, 22)
#define DMAGRP_STATUS_TS_SET(reg, val) DWMAC_REGS_FLD32SET(reg, val, 20, 22)
#define DMAGRP_STATUS_EB(val) DWMAC_REGS_FLD32(val, 23, 25)
#define DMAGRP_STATUS_EB_GET(reg) DWMAC_REGS_FLD32GET(reg, 23, 25)
#define DMAGRP_STATUS_EB_SET(reg, val) DWMAC_REGS_FLD32SET(reg, val, 23, 25)
#define DMAGRP_STATUS_GLI DWMAC_REGS_BIT32(26)
#define DMAGRP_STATUS_GMI DWMAC_REGS_BIT32(27)
#define DMAGRP_STATUS_TTI DWMAC_REGS_BIT32(29)
#define DMAGRP_STATUS_GLPII DWMAC_REGS_BIT32(30)
	uint32_t operation_mode;
#define DMAGRP_OPERATION_MODE_SR DWMAC_REGS_BIT32(1)
#define DMAGRP_OPERATION_MODE_OSF DWMAC_REGS_BIT32(2)
#define DMAGRP_OPERATION_MODE_RTC(val) DWMAC_REGS_FLD32(val, 3, 4)
#define DMAGRP_OPERATION_MODE_RTC_GET(reg) DWMAC_REGS_FLD32GET(reg, 3, 4)
#define DMAGRP_OPERATION_MODE_RTC_SET(reg, val) DWMAC_REGS_FLD32SET(reg, val, 3, 4)
#define DMAGRP_OPERATION_MODE_FUF DWMAC_REGS_BIT32(6)
#define DMAGRP_OPERATION_MODE_FEF DWMAC_REGS_BIT32(7)
#define DMAGRP_OPERATION_MODE_EFC DWMAC_REGS_BIT32(8)
#define DMAGRP_OPERATION_MODE_RFA(val) DWMAC_REGS_FLD32(val, 9, 10)
#define DMAGRP_OPERATION_MODE_RFA_GET(reg) DWMAC_REGS_FLD32GET(reg, 9, 10)
#define DMAGRP_OPERATION_MODE_RFA_SET(reg, val) DWMAC_REGS_FLD32SET(reg, val, 9, 10)
#define DMAGRP_OPERATION_MODE_RFD(val) DWMAC_REGS_FLD32(val, 11, 12)
#define DMAGRP_OPERATION_MODE_RFD_GET(reg) DWMAC_REGS_FLD32GET(reg, 11, 12)
#define DMAGRP_OPERATION_MODE_RFD_SET(reg, val) DWMAC_REGS_FLD32SET(reg, val, 11, 12)
#define DMAGRP_OPERATION_MODE_ST DWMAC_REGS_BIT32(13)
#define DMAGRP_OPERATION_MODE_TTC(val) DWMAC_REGS_FLD32(val, 14, 16)
#define DMAGRP_OPERATION_MODE_TTC_GET(reg) DWMAC_REGS_FLD32GET(reg, 14, 16)
#define DMAGRP_OPERATION_MODE_TTC_SET(reg, val) DWMAC_REGS_FLD32SET(reg, val, 14, 16)
#define DMAGRP_OPERATION_MODE_FTF DWMAC_REGS_BIT32(20)
#define DMAGRP_OPERATION_MODE_TSF DWMAC_REGS_BIT32(21)
#define DMAGRP_OPERATION_MODE_DFF DWMAC_REGS_BIT32(24)
#define DMAGRP_OPERATION_MODE_RSF DWMAC_REGS_BIT32(25)
#define DMAGRP_OPERATION_MODE_DT DWMAC_REGS_BIT32(26)
	uint32_t interrupt_enable;
#define DMAGRP_INTERRUPT_ENABLE_TIE DWMAC_REGS_BIT32(0)
#define DMAGRP_INTERRUPT_ENABLE_TSE DWMAC_REGS_BIT32(1)
#define DMAGRP_INTERRUPT_ENABLE_TUE DWMAC_REGS_BIT32(2)
#define DMAGRP_INTERRUPT_ENABLE_TJE DWMAC_REGS_BIT32(3)
#define DMAGRP_INTERRUPT_ENABLE_OVE DWMAC_REGS_BIT32(4)
#define DMAGRP_INTERRUPT_ENABLE_UNE DWMAC_REGS_BIT32(5)
#define DMAGRP_INTERRUPT_ENABLE_RIE DWMAC_REGS_BIT32(6)
#define DMAGRP_INTERRUPT_ENABLE_RUE DWMAC_REGS_BIT32(7)
#define DMAGRP_INTERRUPT_ENABLE_RSE DWMAC_REGS_BIT32(8)
#define DMAGRP_INTERRUPT_ENABLE_RWE DWMAC_REGS_BIT32(9)
#define DMAGRP_INTERRUPT_ENABLE_ETE DWMAC_REGS_BIT32(10)
#define DMAGRP_INTERRUPT_ENABLE_FBE DWMAC_REGS_BIT32(13)
#define DMAGRP_INTERRUPT_ENABLE_ERE DWMAC_REGS_BIT32(14)
#define DMAGRP_INTERRUPT_ENABLE_AIE DWMAC_REGS_BIT32(15)
#define DMAGRP_INTERRUPT_ENABLE_NIE DWMAC_REGS_BIT32(16)
	uint32_t reserved_20[2];
	uint32_t axi_bus_mode;
#define DMAGRP_AXI_BUS_MODE_UNDEFINED DWMAC_REGS_BIT32(0)
#define DMAGRP_AXI_BUS_MODE_BLEND4 DWMAC_REGS_BIT32(1)
#define DMAGRP_AXI_BUS_MODE_BLEND8 DWMAC_REGS_BIT32(2)
#define DMAGRP_AXI_BUS_MODE_BLEND16 DWMAC_REGS_BIT32(3)
#define DMAGRP_AXI_BUS_MODE_AXI_AAL DWMAC_REGS_BIT32(12)
#define DMAGRP_AXI_BUS_MODE_ONEKBBE DWMAC_REGS_BIT32(13)
#define DMAGRP_AXI_BUS_MODE_RD_OSR_LMT(val) DWMAC_REGS_FLD32(val, 16, 19)
#define DMAGRP_AXI_BUS_MODE_RD_OSR_LMT_GET(reg) DWMAC_REGS_FLD32GET(reg, 16, 19)
#define DMAGRP_AXI_BUS_MODE_RD_OSR_LMT_SET(reg, val) DWMAC_REGS_FLD32SET(reg, val, 16, 19)
#define DMAGRP_AXI_BUS_MODE_WR_OSR_LMT(val) DWMAC_REGS_FLD32(val, 20, 23)
#define DMAGRP_AXI_BUS_MODE_WR_OSR_LMT_GET(reg) DWMAC_REGS_FLD32GET(reg, 20, 23)
#define DMAGRP_AXI_BUS_MODE_WR_OSR_LMT_SET(reg, val) DWMAC_REGS_FLD32SET(reg, val, 20, 23)
#define DMAGRP_AXI_BUS_MODE_LPI_XIT_FRM DWMAC_REGS_BIT32(30)
#define DMAGRP_AXI_BUS_MODE_EN_LPI DWMAC_REGS_BIT32(31)
	uint32_t reserved_2c[11];
	uint32_t hw_feature;
#define DMAGRP_HW_FEATURE_MIISEL DWMAC_REGS_BIT32(0)
#define DMAGRP_HW_FEATURE_GMIISEL DWMAC_REGS_BIT32(1)
#define DMAGRP_HW_FEATURE_HDSEL DWMAC_REGS_BIT32(2)
#define DMAGRP_HW_FEATURE_HASHSEL DWMAC_REGS_BIT32(4)
#define DMAGRP_HW_FEATURE_ADDMACADRSEL DWMAC_REGS_BIT32(5)
#define DMAGRP_HW_FEATURE_PCSSEL DWMAC_REGS_BIT32(6)
#define DMAGRP_HW_FEATURE_SMASEL DWMAC_REGS_BIT32(8)
#define DMAGRP_HW_FEATURE_RWKSEL DWMAC_REGS_BIT32(9)
#define DMAGRP_HW_FEATURE_MGKSEL DWMAC_REGS_BIT32(10)
#define DMAGRP_HW_FEATURE_MMCSEL DWMAC_REGS_BIT32(11)
#define DMAGRP_HW_FEATURE_TSVER1SEL DWMAC_REGS_BIT32(12)
#define DMAGRP_HW_FEATURE_TSVER2SEL DWMAC_REGS_BIT32(13)
#define DMAGRP_HW_FEATURE_EEESEL DWMAC_REGS_BIT32(14)
#define DMAGRP_HW_FEATURE_AVSEL DWMAC_REGS_BIT32(15)
#define DMAGRP_HW_FEATURE_TXOESEL DWMAC_REGS_BIT32(16)
#define DMAGRP_HW_FEATURE_RXTYP1COE DWMAC_REGS_BIT32(17)
#define DMAGRP_HW_FEATURE_RXTYP2COE DWMAC_REGS_BIT32(18)
#define DMAGRP_HW_FEATURE_RXFIFOSIZE DWMAC_REGS_BIT32(19)
#define DMAGRP_HW_FEATURE_RXCHCNT(val) DWMAC_REGS_FLD32(val, 20, 21)
#define DMAGRP_HW_FEATURE_RXCHCNT_GET(reg) DWMAC_REGS_FLD32GET(reg, 20, 21)
#define DMAGRP_HW_FEATURE_RXCHCNT_SET(reg, val) DWMAC_REGS_FLD32SET(reg, val, 20, 21)
#define DMAGRP_HW_FEATURE_TXCHCNT(val) DWMAC_REGS_FLD32(val, 22, 23)
#define DMAGRP_HW_FEATURE_TXCHCNT_GET(reg) DWMAC_REGS_FLD32GET(reg, 22, 23)
#define DMAGRP_HW_FEATURE_TXCHCNT_SET(reg, val) DWMAC_REGS_FLD32SET(reg, val, 22, 23)
#define DMAGRP_HW_FEATURE_ENHDESSEL DWMAC_REGS_BIT32(24)
#define DMAGRP_HW_FEATURE_ACTPHYIF(val) DWMAC_REGS_FLD32(val, 28, 30)
#define DMAGRP_HW_FEATURE_ACTPHYIF_GET(reg) DWMAC_REGS_FLD32GET(reg, 28, 30)
#define DMAGRP_HW_FEATURE_ACTPHYIF_SET(reg, val) DWMAC_REGS_FLD32SET(reg, val, 28, 30)
} dmagrp;

#endif /* MAC_REGS_H */
